The present invention relates to semiconductor integrated circuit device and, more particularly, to a technology which is effective when applied to short channel CMOS device capable of exhibiting high performance when driven at a low voltage.
The CMOSFET (i.e., Complementary MISFET), in which an n-channel MISFET and a p-channel MISFET are formed over a common semiconductor substrate, is applied to almost all devices including microcomputers, gate arrays and memories partly because their power consumption can be reduced and partly because they can be miniaturized to operate at high speed.
A CMOS arrangement is disclosed on pp. 417 to 420 of "A HIGH-PERFORMANCE SUB-HALF MICRON CMOS TECHNOLOGY FOR FAST SRAMS" of IEDM 89, Technical Digest, for example. In this CMOS, the n-channel MISFET and the p-channel MISFET have their gate electrodes made of n-type and p-type polycrystalline silicon, respectively, and their channel regions doped with an impurity having a conductivity type identical to that of the well to adjust their threshold voltage [Vth]. Moreover, an impurity having a conductivity type identical to that of the wells is formed under the channel region so as to prevent the punch-through.